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Most in the industry measure their current-loop bandwidth at 45 degrees of phase margin in order to avoid instability situations. (For reference, an incremental or ABZ encoder provides the shaft angle feedback.) The results shown in both curves of Figure 1 leverage the double sampling technique. Using in-line sensing enables the current to be sampled twice per PWM period during the polarity transition points. By plotting these results against each other, you can see the dramatic difference in bandwidth at a given phase margin between the two control approaches.Įvery one of these tests uses only a 10kHz pulse-width modulation (PWM) carrier frequency and in-line current sensing enabled by INA240 sensors on the low-voltage three-phase gallium nitride (GaN) inverter BoosterPack. In each case, we designed control loops for a target bandwidth and measured the phase margin.
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Figure 1 summarizes the results of FCL tests versus traditional current-loop designs. The most important update to share is the fact that our own in-depth measurements exceeded our previous expectations of “over 3kHz” of control bandwidth versus traditional approaches.
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In early 2018, TI released its second version of the FCL solution, with these updates: The DesignDRIVE C2000 FCL release at that time was targeted for the industrial drive development kit (IDDK) and, while you could measure the loop time with a scope, analyzing the control bandwidth of the current loop meant using an expensive dynamometer and control response analyzer tools in your own laboratory environment. Closing the current loop in less than 1ms had previously been the domain of custom application-specific integrated circuit (ASIC) and field-programmable gate arrays (FPGAs) with parallel data-path architectures. In June 2017, I posted about unprecedented current-loop performance from an off-the-shelf microcontroller (MCU) achieved by the C2000™ family with the fast current loop (FCL) software solution.
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